IMPROVING NOISE TOLERANCE IN CMOS DYNAMIC LOGIC WITH DYNOSAFE

Abstract

Dynamic CMOS circuits are widely used in highperformance digital systems due to their speed and reduced transistor count. However, their susceptibility to noise, charge sharing, leakage, and reduced noise margins poses significant challenges to reliability. This paper presents DYNOSAFE, a novel design approach aimed at enhancing noise tolerance in CMOS dynamic logic. The proposed methodology introduces optimized circuit techniques that mitigate charge leakage and minimize susceptibility to crosstalk and supply noise, without imposing significant performance overhead. Extensive simulation results demonstrate that DYNOSAFE improves noise immunity, maintains signal integrity under varying process, voltage, and temperature (PVT) conditions, and achieves higher robustness compared to conventional dynamic logic implementations. The findings establish DYNOSAFE as a viable and efficient solution for noise-resilient CMOS dynamic circuit design